Today's modern telecommunication depends on high-speed, reliable, and low-cost transmission of digital data. High-speed digital data transmission is a growing and necessary part of everyday communications and supports the function of information appliances such as telephones, televisions, personal computers, and personal data assistants. With the unprecedented advent of the Internet and growing desire for on-demand interactive entertainment, the need for high-speed data transmission is growing rapidly.
High-speed data transmission is dependent upon the network structure through which data is transmitted. The speeds of these networks are realized through the switches and transmission lines between the source and destination of the data. If any aspect of the network is unreliable or delays transmission, the communication quality may be degraded or corrupted. The composition of the data switches within these networks is a primary factor affecting the speed, reliability and cost of telecommunication.
A data switch is a device that has input and output ports to receive and transmit data packets. A data packet arriving at any input port may emerge from any output port depending on the source and destination of the data. The data switch may receive data at an input port, determine which output port it must emerge from, and then transmit the data from that output port in a very small amount of time. The time required for the data switch to complete these steps is known as its propagation delay.
The time required for the data to travel from its original source to a final destination is known as network delay. Network delay is the sum of the propagation delay for all the switches and transmission lines in the communication path between the source and destination of the data. Since Internet, telephone, and television communications occur over great distances, the network delay must be very small and unnoticeable to maintain high communication quality. Data switch propagation delay must be very small since many data switches may be present in the overall data communication path.
Many data switch designs have emerged. With each successive design, switch propagation delay has been reduced. The objective of reducing propagation delay must be achieved in light of other requirements. High-speed data switches must be scalable, and low-cost.
Network providers want to be able to purchase high-speed data switches that have enough ports to accommodate the needs of their current customers. As their need for network bandwidth increases, these customers also want to be able to expand their capacity at a low cost while maintaining high performance. This attribute is known as scalability and is challenging to achieve because high-speed data switches become more costly and less efficient as the number of input or output ports increase.
Although scalability and cost are key data switch requirements, minimum propagation delay is the single most important attribute of high-speed data switches. As modern technology serves to increase the speed of data transmission over conventional transmission lines, data switches are increasingly enhanced to reduce propagation delay. Just to illustrate the evolutionary trends in propagation delay since the 1980's, data switch propagation delays have decreased from 10 milliseconds to under 50 nanoseconds.
Over the past few decades, a number of data switch architectures have been conceived in attempts to achieve scalability, minimize propagation delay and lower cost. These architectures include multiple high-speed bus and matrix switch designs. High-speed bus switches utilize high-speed input-output data port cards that plug into a common bus on the backplane. The data port cards receive data packets on their input ports, determine which output port card the data must emerge from and then route the data to the output port card. This type of architecture suffers significant performance degradation as additional ports are added. Because all of the port cards reside on a common bus, they compete for its use. Consequently, propagation delay is increased as the data port cards must wait to transmit their data to the specified output ports.
Numerous matrix switch architectures exist. These matrix architectures all share common attributes that give them advantages over the bus architecture. Matrix switches are composed of numerous identical switching elements disposed between input and output ports. Each switching element provides a unique transmission path between all input and all output ports. When data arrives at an input port of the matrix switch, the switch determines which output port the data must emerge from, conveys the data through one of the switching elements to the output port, and then transmits the data from the output port.
Matrix architectures are superior to bus architectures with regards to cost, scalability and performance. Since each of the switching elements is identical, their higher volume production decreases cost. Scalability is enhanced because only identical parts (i.e. switch elements, input and output ports) are needed to increase matrix switch capacity and performance is not degraded as capacity is increased. Performance for a matrix switch is superior to bus switches because each input port has numerous paths to any output port. This eliminates internal switch competition.
Matrix switches suffer from a common phenomenon known as collision. Collisions occur when data arrives internally or externally at the same switching element of the matrix switch. These collisions can cause data to be lost or delayed; resulting in reduced overall network performance and reliability. Among matrix switch designs, some architectures are considered to be better than others depending on how well they avoid collisions, while at the same time minimizing propagation delay, facilitating scalability and lowering implementation cost.
Numerous methods for preventing data collisions in matrix switch architectures have been devised. Some utilize data buffering. Data buffering involves adding memory to parts of the matrix switch. The additional memory may be used to store the data in order to avoid a collision. In addition, computer processors can be utilized to determine switch element availability before a switch element is used to transfer data from an input port to an output port. This method is often called load balancing and traditionally utilizes stochastic processes to predict switching element utilization.
Adding memory or microprocessors adds cost and increases propagation delay in matrix switch designs. An improvement of present day matrix switch designs is needed to decrease propagation delays, decrease costs, and improve scalability. To a large degree, the switch matrix design goes a long way toward accomplishing these goals and is superior to other designs such as the bus architecture. However, further improvements are needed to meet the growing needs of today's high-speed communications networks.